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K3S7V2000M-TC
64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM
FEATURES
* JEDEC standard 3.3V power supply * LVTTL compatible with multiplexed address * Address: Row address: RA0 ~ RA12 Column address: CA0 ~ CA7 (x32): CA0 ~ CA8 (x16) * Switchable organization 4,194,304 x 16(word mode) / 2,097,152 x 32(double word mode) * All inputs are sampled at the rising edge of the system clock * Read Performance at memory point of view @33MHz 4-1-1-1 (RAS Latency=1, CAS Latency=3) @50MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4) @66MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4) @83MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5) @100MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5) * tSAC : 6ns * Default mode by user requirement * MRS cycle with address key programs -. RAS Latency(1 & 2) -. CAS Latency(3 ~ 6) -. Burst Length : 4, 8 -. Burst Type : Sequential & Interleaved * DQM for data-out masking * Package :86TSOP2 - 400
Synch. MROM
GENERAL DESCRIPTION
The K3S7V2000M-TC is a synchronous high bandwidth mask programmable ROM fabricated with SAMSUNGs high performance CMOS process technology and is organized either as 4,194,304 x16bit(word mode) or as 2,097,152 x32bit(double word mode) depending on polarity of WORD pin.(see pin function description). Synchronous design allows precise cycle control, with the use of system clock, I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part NO. K3S7V2000M-TC10 K3S7V2000M-TC12 K3S7V2000M-TC15 K3S7V2000M-TC20 K3S7V2000M-TC30 MAX Freq. 100MHz 83MHz 66MHz 50MHz 33MHz LVTTL 86TSOP2 Interface Package
FUNCTIONAL BLOCK DIAGRAM
Q0 Q16
.
Output
.
.
Buffer
Q15
Q31
Row Decoder
Sense AMP.
Row Buffer
4M x 16 /2M x 32 Cell Array
Address Register
CLK ADD
Column Decoder Col. Buffer
LRAS
Latency & Burst Length
LCKE LRAS LMR LCAS Timing CLK CKE MR Register RAS
Programming Register
CAS
CS
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
K3S7V2000M-TC
PIN CONFIGURATION (TOP VIEW)
Synch. MROM
VDD Q0 VDDQ Q16 Q1 VssQ Q17 Q2 VDDQ Q18 Q3 VssQ Q19 MR# VDD DQM NC CAS# RAS# CS# WORD# A12 A11 A10 A0 A1 A2 NC VDD NC Q4 VssQ Q20 Q5 VDDQ Q21 Q6 VssQ Q22 Q7 VDDQ Q23 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
Vss Q31 VssQ Q15 Q30 VDDQ Q14 Q29 VssQ Q13 Q28 VDDQ Q12 NC Vss NC NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 NC Vss NC Q27 VDDQ Q11 Q26 VssQ Q10 Q25 VDDQ Q9 Q24 VssQ Q8 Vss
86TSOPII - 400 (0.5 mm Pin Pitch)
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
K3S7V2000M-TC
PIN FUNCTION DESCRIPTION
PIN CLK CS NAME System Clock Chip Select INPUT FUNCTION Active on the rising edge to sample all inputs.
Synch. MROM
Disables or enables device operation by masking or enabling all inputs except CLK and CKE. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down in standby mode. Row / Column addresses are multiplexed on the same pins. Row address: RA0 ~ RA12, Column address: CA0 ~ CA7 (x32): CA0 ~ CA8 (x16) Latches row addresses on the rising edge of the CLK with RAS low. Enables row access Latches column addresses on the rising edge of the CLK with CAS low. Enables column access. Enables mode register set with MR low. (Simultaneously CS,RAS and CAS are low)
CKE
Clock Enable
A0 ~ A12
Address
RAS CAS MR Q0 ~ Q31 VDD/VSS VDDQ/VSSQ WORD DQM N.C
Row Address Strobe Column Address Strobe Mode Register Set Data Output Power Supply/Ground Data Output Power/ Ground x32/x16 Mode Selection Data-out Masking No Connection
Power and ground for the input buffers and the core logic. Power and ground for the output buffers. Double word mode/word mode, depending on polarity of WORD pin. Should be set before CAS enabling. It works similar to OE during read operation. This pin is recommended to be left No Connection on the device.
Note1. VDD and VDDQ is same voltage.
K3S7V2000M-TC
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on VDD Relative to Vss Voltage on Any Pin Relative to Vss Operating Temperature Storage Temperature Short circuit current Power Dissipation Symbol VDD, VDDQ VIN, VOUT TA TSTG IOS PD Min -0.5 -0.5 0 -55 Max 4.6
Synch. MROM
Unit V V C C mA W
VDD + 0.54.6 70 125 50 1
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition.
DC OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS, TA=0 to 70C)
Parameter Supply Voltage Supply Voltage(Ground) Symbol VDD, VDDQ VSS,VSSQ Min 3.0 0 Typ 3.3 0 Max 3.6 0 Unit V V
DC CHARACTERISTICS
Parameter Standby Current ( Note3) Active Standby Current Burst Mode Operating Current Input Leakage Current Output Leakage Current (Dout Disabled) Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level (Logic 1) Output Low Voltage Level (Logic 0) Symbol ICC3P ICC3PS ICC3N ICC4 IIL IOL VIH VIL VOH VOL Min -10 -10 2.0 -0.3 2.4 Max 150 150 50 100 10 10 VDD + 0.3 0.8 0.4 Unit uA uA mA mA uA uA V V V V Test Condition CKEVIL(Max), tCC=Min CKE=0, tCC=Min CSVIH(Min), tCC=Min, All Outputs Open tCC=Min, All Outputs Open 0VVINVDD + 0.3V Pins not under test=0V (0VVOUTVDD Max) Q# in High-Z (Note1) (Note2) IOH=-2mA IOL=2mA
Note : 1. VIH(Max)=4.6V for pulse width10ns acceptable, pulse width measured at 50% of pulse amplitude. 2. VIL(Min)=-1.5V for pulse width10ns acceptable, pulse width measured at 50% of pulse amplitude. 3. The condition is the same as Self Refresh Mode of SDRAM, that is, in this case CS,RAS,CAS have to be set to Low, MR has to be set to High.
K3S7V2000M-TC
Parameter Timing Reference Levels of Input/Output Signals Input Signal Levels Transition Time (Rise & Fall) of Input Signals Output Load Value 1.4V
Synch. MROM
AC OPERATING TEST CONDITIONS(TA = 0 to 70C, VDD = 3.3V0.3V, unless otherwise noted.)
VIH/VIL=2.4V/0.4V tr/tf=1ns/1ns LVTTL
Note : If CLK transition time is longer than 1ns, timing parameters should be compensated. Add [(tr+tf)/2-1]ns for transition time longer than 1ns. Transition time is measured between VIL(Max) and VIH(Min).
3.3V
Vtt=1.4V
1200 Output 870 50pF VOH (DC)=2.4V, IOH=-2mA VOL (DC)=0.4V, IOL=2mA Output Z0=50
50
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETERS
(AC operating conditions unless otherwise noted) Parameter CLK Cycle Time CLK to Valid Output Delay Data Output Hold Time CLK High Pulse Width CLK Low Pulse Width Row-active to Row-active Input Setup Time Input Hold Time CLK to Output in Low-Z CLK to Output in High-Z Transition Time Valid CAS Enable to Valid CAS Enable Symbol tCC tSAC tOH tCH tCL tRC tSS tSH tSLZ tSHZ tT tVCVC up to 100MHz Min 10 2 3 3 10 2 1 0 0.1 8 6 7 10 Max up to 83MHz Min 12 2 3.5 3.5 10 3 1 0 0.1 8 6 8 10 Max up to 66MHz Min 15 2 4 4 8 4 2 0 0.1 7 Max 6 10 10 up to 50 Mhz Min 20 2 6.5 6.5 8 4 2 0 0.1 7 Max 6 15 10 ns ns ns ns ns clks ns ns ns ns ns clks 2 1 Unit Notes
Note : 1. These tRC values are for BL=8. For BL=4, tRC=6 clks for up to 100MHz, tRC=6 clks for up to 83MHz, tRC=4 clks for up to 66MHz, tRC=4 clks for up to 50MHz, and tRC=3 clks for up to 33MHz. RAS latency increase means, a simultaneous tRC increase in the same number of cycles. ( If RAS latency is 3 clks, tRC is 12 clks for BL=8.) Refer to attached technical note for gapless operation. 2. These tVCVC values are for BL=8. For BL=4, tVCVC=4clks for up to 100MHz, tVCVC=4clks for up to 83MHz, tVCVC=3clks for up to 66MHz, tVCVC=3clks for up to 50MHz, and tVCVC=2clks for up to 33MHz. Refer to attached technical note for gapless operation.
K3S7V2000M-TC
CAPACITANCE(TA=25C, f=1MHz)
Parameter Input Capacitance Output Capacitance Symbol CIN COUT Min Max 5 7
Synch. MROM
Unit pF pF
FUNCTION TRUTH TABLE
Command Register Mode Register Set
CKEn-1 CKEn CS RAS CAS MR DQM Add. WORD Notes
H H H H H H L H
X X X X X L H
L L L L L X X
L L H H L X X X
L H L H H X X
L H H L L X X
X X X X X X X V
Code RA CA X X X X X CA X X X CA
X X X X X X X
1
Row Active Row Access & Latch Row Access& Latch Read Burst Stop Power Down & Clock Suspend DQM Illegal
(Write on Synch.DRAM) (Refresh on Synch.DRAM)
Column Access & Latch
(Burst Stop on Synch.DRAM) (Precharge on Synch.DRAM)
Two Standby Mode
Entry Exit
2 3
H H H H
X X X X X
L L H L L
H L X H H
L L X H L
L H X H H
X X X X X
X X X X H L 5 4
No Operation Command
Organization Control
H
(V=Valid, X=Don't Care, H=Logic High, L=Logic Low) Abbreviations (RA: Row Address, CA: Column Address, NOP: No Operation Command, DWM: Double Word Mode, WM: Word Mode) Notes : 1. A0 ~ A6: Program keys (@MRS). After power up, mode register set, can be set before issuing other input command. After the mode register set command is completed, no new commands can be issued for 3 CLK Cycles, and CS or MR state must be defined "H" within 3 CLK cycles. Refer to the Mode Register Field Table 2. In the case CKE is low, two standby modes are possible. Those are stand-by mode in power-down. Power Down: CKE="L" (at all the parts except the range of Row Active, Read & Data out) Clock Suspend: CKE="L" (at the range of Row Active, Read & Data Out) 3. DQM sampled at rising edge of a CLK makes a Hi-Z state the data-out state, delayed by 2CLK cycles. 4. Precharge command on Synch.DRAM can be used for Burst Stop operation during burst read operation only. 5. Mode selection control is decided simultaneously with column access start, and according to the polarity of WORD pin, "H" state is DWM, "L" state is WM.
K3S7V2000M-TC
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address Function A6 RAS Latency RAS Latency A6 0 1 Length 1 2 A5 0 0 0 0 1 1 1 1 A4 0 0 1 1 0 0 1 1 A5 A4 CAS Latency CAS Latency A3 0 1 0 1 0 1 0 1 Length Reserved Reserved 3 4 5 6 Reserved Reserved A3 A2 Burst Type Burst Type A2 0 1 Type Sequential Interleave
Synch. MROM
A1 Burst Length Burst Length A1 0 0 1 1 A0 0 1 0 1
A0
Length Reserved 4 8 Reserved
Notes : -. After power up, when user wants to change mode register set, user must exit from power down mode and start mode register set before entering normal operation mode.
ADDRESSING MAP
(1) WORD = "H" : x32 Organization
Function Row Address Column Address A0 RA0 CA0 A1 RA1 CA1 A2 RA2 CA2 A3 RA3 CA3 A4 RA4 CA4 A5 RA5 CA5 A6 RA6 CA6 A7 RA7 CA7Note A8 RA8 X A9 RA9 X A10 RA10 X A11 RA11 X A12 RA12 X
Note : Column Address MSB (at x32 organization)
(X=Don't Care)
(2) WORD="L" : x16 Organization
Function Row Address Column Address A0 RA0 CA0 A1 RA1 CA1 A2 RA2 CA2 A3 RA3 CA3 A4 RA4 CA4 A5 RA5 CA5 A6 RA6 CA6 A7 RA7 CA7 A8 RA8 CA8Note A9 RA9 X A10 RA10 X A11 RA11 X A12 RA12 X
Note : Column Address MSB (at x16 organization)
(X=Don't Care)
(3) Each address is arranged as follows
for X32 operation, Address Register Address MSB AR20 RA12 AR19 RA11 AR18 RA10 ... ... AR9 RA1 AR8 RA0 AR7 CA7 AR6 CA6 ...
...
LSB AR3 CA3 AR2 CA2 AR1 CA1 BL=4 AR0 CA0
BL=8 for X16 operation, when CA8 is set to Low, data belonging to 0~15th registers are output to Q0~Q15 pins, and when CA8 is set to High, data belonging to16~31th registers are output to Q0~Q15 pins.
* Initial Address - BL=4(CA0,CA1) - BL=8(CA0,CA1,CA2)
K3S7V2000M-TC
x32 operation (double word mode)
Column Address CA7 0 0 0 0 0 0 CA6 0 0 0 0 0 0 CA5 0 0 0 0 0 0 CA4 0 0 0 0 0 0 CA3 0 0 0 0 0 0 CA2 0 0 0 0 1 1 CA1 0 0 1 1 0 0 CA0 0 1 0 1 0 1 A B C D E F A B C D E F A B C D E F A B C D E F D15 ~ D0 (Hexadecimal)
Synch. MROM
D31 ~ D16 (Hexadecimal) 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
x16 operation (word mode)
Column Address CA8 0 0 0 0 0 0 CA7 0 0 0 0 0 0 CA6 0 0 0 0 0 0 CA5 0 0 0 0 0 0 CA4 0 0 0 0 0 0 CA3 0 0 0 0 0 0 CA2 0 0 0 0 1 1 CA1 0 0 1 1 0 0 : 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 1 2 0 1 2 0 1 2 D31 ~ D16 D31 ~ D16 D31 ~ D16 CA0 0 1 0 1 0 1 A B C D E F A B C D E F A B C D E F A B C D E F D15 ~ D0 D15 ~ D0 D15 ~ D0 D15 ~ D0 D15 ~ D0 D15 ~ D0 Data Out (Hexadecimal) Comment
BURST SEQUENCE(BURST LENGTH = 4)
Initial address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 2 3 0 1 3 2 1 0 Sequential Interleave
BURST SEQUENCE(BURST LENGTH = 8)
Initial address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 Sequential Interleave
K3S7V2000M-TC
DEVICE OPERATIONS
CLOCK (CLK)
Synch. MROM
The clock input is used as a reference for SMROM operation. A square wave signal(CLK) must be applied externally at cycle time tCC. All operations are synchronized to the rising edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high, all inputs are assumed to be in valid state (low or high) for the duration of set-up and hold time around the positive edge of the clock for proper functionality and ICC specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock into the SMROM and is asserted high during all cycles, except for power down, stand-by and clock suspend mode. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen for as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. The SMROM remains in the power down mode ignoring other inputs for as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1 CLK + tSS" before the rising edge of the clock, then the SMROM becomes active from the same clock edge accepting all the input commands.
NOP and DEVICE DESELECT
When RAS, CAS and MR are high, the SMROM performs no operation (NOP). NOP does not initiate any new operation. Device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, MR and all the address inputs are ignored. In addition, entering a mode register set command in the middle of a normal operation, results in an illegal state in SMROM.
POWER-UP
The following power-up sequence is recommended. 1. Apply power and start clock, Attempt to maintain MR, CKE and DQM inputs to pull them high and the other pins are NOP condition at the inputs before or along with VDD(and VDDQ) supply. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 20us. 3. When user wants to change the default mode register set values, perform a MODE REGISTER SET cycle to program the RAS latency, CAS latency, burst length and burst type. 4. At the end of three clock cycles after the mode register set cycle, the device is ready for operation. When the above sequence is used for power-up, all outputs will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence.
MODE SELECTION CONTROL
Mode selection control is decided simultaneously with column access, and according to WORD pin voltage level. High level signifies double word mode(x32) and low level signifies word mode(x16).
ADDRESS DECODING
The address bits required to decode one of the available cell locations out of the total depth are multiplexed onto the address select pins and latched by externally applying two commands. The first command, RAS asserted low, latches the row address into the device. A second command, CAS asserted low, subsequently latches the column address.
K3S7V2000M-TC
DEVICE OPERATIONS
MODE REGISTER SET (MRS)
Synch. MROM
The mode register stores the data for controlling the various operating modes of SMROM. It programs the RAS latency, CAS latency, burst length, burst type. On power-up, the mode register is set to the default value defined by the user requirement. When and if the user wants to change its values, the user must exit from power down mode and start mode register set before entering normal operation mode. The mode register is reprogrammed by asserting low on CS, RAS, CAS and MR (The SMROM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ A7 in the same cycle as CS, RAS, CAS and MR going low is the data written in the mode register. Three clock cycles are required to complete the program in the mode register, therefore after mode register set command is completed, no new commands can be issued for 3 clock cycles and CS or MR must be fixed to high within 3 clock cycles. The mode register is divided into various fields depending on functionality. The burst length field uses A0 ~ A1, burst type uses A2, CAS latency (read latency from column address) uses A3 ~ A5, RAS latency uses A6 (RAS to CAS delay). Refer to the table for specific codes for various burst length, burst type, CAS latencies and RAS latencies.
LATENCY
There are latencies between the issuance of a Row active command and when data is available on the I/O buffers. The RAS to CAS delay is defined as the RAS latency. The CAS to data out delay is the CAS latency. The CAS and RAS latencies are programmable through the mode register. RAS latencies of 1 and 2, and CAS latencies of 3 through 6 are supported. It is understood that some RAS and CAS latency values are reserved for future use, and may not be available in the first generation for SMROM. The followings are the supported minimum values in the first generation. RAS latency=2, and CAS latency=5 for 100MHz operation, and RAS latency=2, and CAS latency=5 for 83MHz operation, and RAS latency=1, and CAS latency=4 for 66MHz operation, and RAS latency=1, and CAS latenecy=4 for 50MHz operation, and RAS latency=1, and CAS latenecy=3 for 33MHz operation.
DQM OPERATION
The DQM is used to mask output operations when a complete burst read is not required. It works similar to OE during a read operation. The read latency is two cycles from DQM, which means DQM masking occurs two cycles later in the read cycle. DQM operation is synchronous with the clock. The masking occurs for a complete cycle. (Also refer to the DQM timing diagram)
BURST READ
The burst read command is used to access a burst of data on consecutive clock cycles from an active row state. The burst read command is issued by asserting low CS and CAS with MR being high on the rising edge of the clock. The first output appears in CAS latency number of clock cycles after the issuance of the burst read command. The burst length, burst sequence and latency from the burst read command are determined by the mode register which is already programmed. Burst read can be initiated on any column address of the active row. The output goes into high-impedance at the end of the burst, unless a new burst read is initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read.
K3S7V2000M-TC
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. MRS
Mode Register Set CLK CMD MRS
Note 1 3CLK
Synch. MROM
ACT
2. CLOCK Suspend
Clock Suspended During Burst Read (BL=4) CLK CMD CKE
Masked by CKE
RD
Internal CLK
Data
Q0
D0 Q1
Q2
Q3
Suspended Dout
: This command do not be activated.
3. Clock Suspend Exit & power Down Exit
1) Clock Suspend Exit CLK CKE Internal CLK CMD RD
tSS
2) Power Down Exit CLK CKE Internal CLK CMD NOP ACT
tSS
Note : 1. After mode register set command is completed, no new commands can be issued for 3 clock cycles, and MR or CS should be fixed "H" within a minimum of 3 clock cycles.
K3S7V2000M-TC
4. DQM Operation
1) Read Mask (BL=4) CLK CMD DQM Data(CL2) Data(CL3) Data(CL4) Q0 Q1 Q0
Masked by DQM Hi-Z
Synch. MROM
RD
Q3 Q2 Q1
Hi-Z Hi-Z
Q3 Q2 Q3
DQM to Data-out Mask = 2CLKs 2) DQM with Clock Suspended (BL=8) CLK CMD CKE DQM
Note 1
RD
Data(CL2) Data(CL3) Data(CL4)
Q0
D1 Q1 Q0
Hi-Z Hi-Z Hi-Z
Q3 Q2 Q1
Hi-Z Hi-Z Hi-Z
Q5 Q4 Q3
Hi-Z Hi-Z Hi-Z
Q7 Q6 Q5
Q8 Q7 Q6 Q8 Q7
*Note : 1. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"
K3S7V2000M-TC
Synch. MROM
Read Cycle I : Normal @RAS Latency=2, CAS Latency=5, Burst Length=4
tCH 4
0 CLK
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tCC CKE tRC
tCL
HIGH
tSH CS RAS Latency tSH RAS tSS tSS
CAS
tSH ADDR RAa tSS tRC=6 clocks at BL=4
*Note 1
CAa
RAb
CAb
tOH Data Qa0 Qa1 Qa2 Qa3 tSAC tSHZ Qb0 Qb1 Qb2 Qb3
MR
Row Active
Read
Row Active
Read
: Don't Care
*Note: 1. When the burst length is 4 at 100MHz, tRC is equal to 6 clock cycles.
K3S7V2000M-TC
Synch. MROM
Read Cycle II : Consecutive Column Access @RAS Latency = 2, CAS Latency=5, BL = 4
tCH
0
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tCC CKE
tCL
HIGH
tSH CS RAS Latency tSH RAS tSS tSS
CAS
tSH ADDR RAa tSS tVCVC=4 clocks at BL=4 tOH Data Burst Length=4 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 tSAC tSHZ CAa CAb
*Note 1
MR
Row Active
Read
Read : Don't Care
Note: When column access is initiated beyond tVCVC, 1. at BL=4, CAa access read is completed, CAb access read begins.
K3S7V2000M-TC
Synch. MROM
Read Cycle III : Clock Suspend @RAS Latency = 2, CAS Latency=5, Burst Length=4
tCH 4
0 CLK
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tCC CKE
tCL
*Note 1
Internal CLK
CS RAS Latency tSH RAS tSS
CAS
tSH ADDR RAa tSS tVCVC= 4 clocks at BL=4
*Note 2
CAa
Data
Burst Length=4
Qa0
Qa1
Qa2 Qa3
MR
Row Active
Read
Clock Suspend Resume
: Don't Care
Note : 1. From next clock after CKE goes low, clock suspension begins. 2. For clock suspension, data output state is held & maintained.
K3S7V2000M-TC
Synch. MROM
Read Interrupted by Precharge Command & Burst Read Stop Cycle @Burst Length=8
0 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
CAb
Note1
Note1
CL=2 Data CL=3
Qa0 Qa1 Qa2 Qa3 Qa4
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5
Note2
Note2
Qa0 Qa1 Qa2 Qa3 Qa4
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5
MR
DQM
*Note1, 2
Row Active
Read
Burst Stop
Read
Precharge : Don't Care
*Note : 1. The burst stop command is valid at every page burst length. The data bus goes to High-Z after the CAS latency from the burst stop command is issued. 2. The interval between read command (column address presented) and burst stop command is 1 cycle(min).
K3S7V2000M-TC
Power Down & Clock Suspend Cycle :
@RAS Latency = 2, CAS Latency=5, Burst Length=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Synch. MROM
16
17
18
19
tSS CKE
*Note 1 *Note 1
Power Down
Clock Suspend
CLK
(internal)
CS
RAS
CAS
*Note 2
tSH CAa
ADDR
NOP RAa tSS
Data
Data Hi-Z State
Qa0 Qa1
Qa2
Qa3
MR
(High)
Row Active Read Power-down Entry Power-down Exit Clock Suspend Entry Clock Suspend Exit : Don't Care
Note : 1. From next clock after CKE goes low, clock suspend and power down begins. 2. After power down exit, NOP should be issued and new command can be issued after 1clock.
K3S7V2000M-TC
Mode Register Set:
@RAS Latency = 2, CAS Latency=5, Burst Length=4
0 CLK tCC CKE tCL 1 2 3 tCH 4 5 6 7 8 9 10 11 12 13 14 15
Synch. MROM
16
17
18
19
HIGH
tSH CS tSS
RAS RAS Latency
CAS
ADDR
Code
RAa
CAa
Data
Data Hi-Z State
Qa0 Qa1 Qa2 Qa3
MR
MRS
Row Active
: Don't Care
Note : 1. After the mode register set is completed, no new commands can be issued for 3CLK cycles. 2. After power up, necessarily mode register set should be completed at least one time and CS or MR must be fixed "H" within 3clock cycles, and when user wants to change mode register set, user must exit from power down mode and start mode register set before chip enters normal operation mode.
K3S7V2000M-TC
FUNCTION TRUTH TABLE
Current State After Power Up* Input Signal CKE L H H H Row Active H H L CS X L L L L L X RAS X L L L H L X CAS X H L H L L X MR X H L H H L X Add. X RA Code RA CA Code X -. Clock Suspend -. Power Down
Synch. MROM
Next State Operation
-. Row Active ; latch RA -. Mode Register Set -. If consecutive row access is issued within tRCmin. without CAS enabling, only the final RA is valid. -. Begin READ ; latch CA Illegal *
H
L
L
H
H
RA
-. Row Access in Read State, within the tRC, previous read is ignored and new row is activated. beyond the tRC, previous read is completed and new read begins. -. Consecutive Column Access, within the tVCVC, only the final CA is valid and the previous burst read is ignored. Beyond the tVCVC, the previous read is completed and new read begins. -. NOP (After Burst Read) / Read Interrupt -. NOP (After Burst Read) / Read Interrupt Illegal * -. Clock Suspend / Power Down -. Low Power Consumption Mode NOP Illegal Illegal
READ
H
L
H
L
H
CA
H H H L Any State Any State Any State L H H H
mode.
L L L X L L L L
L H L X L H L H
H H L X L H L L
L L L X H H H L
X X Code X X X X CA
* : After the power up, when user wants to change MR set, user must exit from power down mode and start MR set before chip enters normal operation
K3S7V2000M-TC
Technical Notes
1. Frequency vs. AC Parameter Relationship Table
K3S7V2000M-TC10
Burst Length 4 RAS Latency 2 6 5 8 2 6 11 7 10 CAS Latency 5 tRCmin. 6
Synch. MROM
( unit : number of clock )
tVCVCmin. 4* 5 8* 9
K3S7V2000M-TC12
Burst Length 4 RAS Latency 2 6 5 8 2 6 11 7 10 CAS Latency 5 tRCmin. 6
( unit : number of clock )
tVCVCmin. 4* 5 8* 9
K3S7V2000M-TC15
Burst Length RAS Latency CAS Latency 4 1 4 4 2 5 6 4 1 8 4 2 5 6 9 10 11 5 6 5 6 7 8* 9 10 5 6 tRCmin. 4* 5 6
( unit : number of clock )
tVCVCmin. 3/ 4* 4* 5 3/ 4* 4* 5 7/ 8* 8* 9 7/8* 8* 9
K3S7V2000M-TC
K3S7V2000M-TC20
Burst Length RAS Latency CAS Latency 4 1 4 4 2 5 6 4 1 8 4 2 5 6 9 10 11 5 6 5 6 7 8* 9 10 5 6 tRCmin. 4* 5 6
Synch. MROM
( unit : number of clock )
tVCVCmin. 3/ 4* 4* 5 3/4* 4* 5 7/8* 8* 9 7/ 8* 8* 9
K3S7V2000M-TC30
Burst Length RAS Latency CAS Latency 3 4 1 5 6 4 3 2 4 5 6 3 4 1 5 6 8 3 4 2 5 6 Note : Above tables are not specification values, rather actual values. There are no gapless operations for CAS latency 6. * : Minimum clocks for Gapless Operation. 10 11 8* 9 9 10 4* 5 6 7 7/ 8* 8* 5 6 tRCmin. 3/ 4* 4*
( unit : number of clock )
tVCVCmin. 2/ 4* 3/ 4* 4* 5 2/4* 3/4* 4* 5 6/ 8* 7/ 8* 8* 9 6/8* 7/8* 8* 9
K3S7V2000M-TC
Technical Notes (Continuous)
2. CAS Interrupt
Read interrupted by Read (BL=4)Note 1 CLK CMD ADD Data(CL2) Data(CL3) Data(CL4)
Note 2
Synch. MROM
RD A
RD B QB0 QB1 QB0 QB2 QB1 QB0 QB3 QB2 QB1 QB3 QB2 QB3
*Note : 1. By " Interrupt", It is meant to stop burst read by external command before the end of burst. By "CAS Interrupt", to stop burst read by CAS access. 2. CAS to CAS delay. (=1CLK)
3. Read interrupt operation by issuing the precharge or Burst Stop Command
CASE I ) Issued read Interrupt command during burst read operation period.
CLK CMD Data(CL2) Data(CL3) Data(CL4) RD PRE
Note 1
CLK CMD Q1 Q0 Q1 Q0 Q1 Data(CL2) Data(CL3) Data(CL4) RD
STOP
Note 1
Q0
Q0
Q1 Q0 Q1 Q0 Q1
CASE II ) Issued read Interrupt command between read command and data out.
CLK CMD Data(CL2) Data(CL3) Data(CL4) RD PRE
Note 2
CLK CMD Q0 Q0 Q0 Data(CL2) Data(CL3) Data(CL4) RD
STOP
Note 2
Q0 Q0 Q0
*Note : 1. The data bus goes to High-Z after CAS Latency from the burst stop (or precharge) command. 2. Valid output data will last up to CL-1 clock cycle from PRE command.
K3S7V2000M-TC
4. Read cycle depending on tRC
@ RL = 2, CL = 5, BL = 4 ; 100MHz
CLK
tRC(min)=6 tCC=10ns
Synch. MROM
CMD ACT
RDa
ACT ACT
RDb
CASE I ) CASE II ) CASE III )
RDb ACT
RDb
CASE I ) CASE II ) CASE III )
High-Z Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Qa3
Qb0
Qb1 Qb0
Qb2 Qb1 Qb0
Qb3 Qb2 Qb1 Qb3 Qb2 Qb3
@ RL = 2, CL = 5, BL = 4 ; 83MHz
CLK
tRC(min)=6 tCC=12ns
CMD ACT
RDa
ACT ACT
RDb
CASE I ) CASE II ) CASE III )
RDb ACT
RDb
CASE I ) CASE II ) CASE III )
High-Z Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Qa3
Qb0
Qb1 Qb0
Qb2 Qb1 Qb0
Qb3 Qb2 Qb1 Qb3 Qb2 Qb3
@ RL = 1, CL = 4, BL = 4 ; 66MHz
CLK
tRC(min)=4 tCC=15ns
CMD ACT RDa
ACT RDb ACT
CASE I ) CASE II ) CASE III )
RDb
ACT RDb CASE I ) CASE II ) CASE III ) High-Z Qa0 Qa0 Qa1 Qa1
Qb0 Qb1 Qa2 Qa2 Qa3 Qa3 Qb0
Qb2 Qb1 Qb0
Qb3 Qb2 Qb1 Qb3 (Gapless Operation) Qb2 Qb3
K3S7V2000M-TC
@ RL = 1, CL = 4, BL = 4 ; 50MHz
CLK
tRC(min)=4 tCC=20ns
Synch. MROM
CMD ACT RDa
ACT RDb
CASE I ) CASE II) CASE III)
ACT RDb
ACT RDb CASE I ) CASE II ) CASE III ) Qa0 Qa0 Qa1 Qa1
Qb0 Qa2 Qa2 Qa3 Qa3
Qb1 Qb0
Qb2 Qb1 Qb0
Qb3 (Gapless Operation) Qb2 Qb1 Qb3 Qb2 Qb3
: Invalid Data
@ RL = 1, CL = 3, BL = 4 ; 33MHz
CLK
tRC(min)=3 tCC=30ns
CMD ACT RDa ACT RDb ACT
CASE I) CASE II) CASE III)
RDb ACT
RDb
CASE I ) CASE II ) CASE III ) Qa0 Qa0
Qb0 Qa1 Qa2 Qa1 Qa2
Qb1
Qb2 Qb1
Qb3 Qb2 Qb1 Qb3 (Gapless Operation) Qb2 Qb3
: Invalid Data
Qa3
Qb0
K3S7V2000M-TC
5. Read cycle depending on tVCVC
@ RL = 2, CL = 5, BL = 4 ; 100MHz
CLK
tVCVC=4 tCC=10ns
Synch. MROM
CMD ACT
RDa
RDb
CASE I)
RDb CASE II) RDb CASE III) CASE I ) CASE II ) CASE III ) Qb0 Qb1 Qb2 Qb3 (Gapless Operation) Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
: Invalid Data
@ RL = 2, CL = 5, BL = 4 ; 83MHz
CLK
tVCVC=4 tCC=12ns
CMD ACT
RDa
RDb
CASE I)
RDb CASE II) RDb CASE III) CASE I ) CASE II ) CASE III ) Qb0 Qb1 Qb2 Qb3 (Gapless Operation) Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
: Invalid Data
@ RL = 1, CL = 4, BL = 4 ; 66MHz
CLK
tVCVC=3 tCC=15ns
CMD ACT RDa
RDb
CASE I)
RDb CASE II) RDb CASE III) CASE I ) CASE II ) CASE III ) Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qb2 Qb1 Qb2 Qb3 (Gapless Operation) Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
: Invalid Data
K3S7V2000M-TC
@ RL = 1, CL = 4, BL = 4 ; 50MHz
CLK
tVCVC=3 tCC=20ns
Synch. MROM
CMD ACT RDa
RDb
CASE I) CASE II) CASE III)
RDb
RDb
CASE I ) CASE II ) CASE III )
Qb0 Qb1 Qa0 Qa1 Qa2
Qb2 Qb3 Qb1 Qb2 Qb3 (Gapless Operation)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
: Invalid Data
@ RL = 1, CL = 3, BL = 4 ; 33MHz
CLK
tVCVC=2 tCC=30ns
CMD ACT RDa RDb
CASE I) CASE II) CASE III)
RDb
RDb CASE I ) CASE II ) CASE III )
Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa0 Qa1 Qa2 Qb1 Qb2 Qb3 Qb1 Qb2 Qb3
: Invalid Data
K3S7V2000M-TC
6. Read Cycle depending on tVCVC and tRC
@ RL = 1, CL = 4, BL = 4 ; 50MHz (Gapless Operation)
CLK
tVCVC=4 tCC=20ns
Synch. MROM
CMD ACT RDa
RDb
ACT RDc
RDd
ACT RDe
Read out
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Qc3 Qd0 Qd1 Qd2
@ RL = 1, CL = 4, BL = 4 ; 50MHz
CLK
tVCVC=4 tCC=20ns
CMD ACT RDa
RDb
ACT RDc
RDd
ACT RDe
RDf
Read out
Qa0 Qa1 Qa2 Qa3
Qc0 Qc1 Qc2 Qc3
Qe0
: Invalid Data
@ RL = 1, CL = 4, BL = 4 ; 50MHz
CLK
tVCVC=4 tCC=20ns
CMD ACT RDa
RDb ACT RDc
RDd ACT RDe
RDf
Read out
Qa0 Qa1 Qa2
Qc0 Qc1 Qc2
Qe0 Qe1 Qe2
: Invalid Data

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